Evaluation Of New Testing Methodologies For Innovative System Architectures H/F - 38

Le CEA est un acteur majeur de la recherche, au service des citoyens, de l'économie et de l'Etat.

Il apporte des solutions concrètes à leurs besoins dans quatre domaines principaux : transition énergétique, transition numérique, technologies pour la médecine du futur, défense et sécurité sur un socle de recherche fondamentale. Le CEA s'engage depuis plus de 75 ans au service de la souveraineté scientifique, technologique et industrielle de la France et de l'Europe pour un présent et un avenir mieux maîtrisés et plus sûrs.

Implanté au coeur des territoires équipés de très grandes infrastructures de recherche, le CEA dispose d'un large éventail de partenaires académiques et industriels en France, en Europe et à l'international.

Les 20 000 collaboratrices et collaborateurs du CEA partagent trois valeurs fondamentales :

- La conscience des responsabilités
- La coopération
- La curiositéTesting is a fundamental phase of design and production of integrated circuits. It ensures not only the quality of electronic chips, but also compliance with security constraints required by several applications. Memory Built-In Self-Test (MBIST) and Logic Built-in Self-Test (LBIST) are widely used techniques for testing circuit memories and logic. It entails integrating extra hardware components around the memory, which are capable of efficiently performing testing operations. On the other hand, Near Memory Computing (NMC) is emerging as a promising solution to accelerate processing and to reduce energy consumption in integrated circuits. To study these architectures, the CEA has developed the Computational-SRAM (C-SRAM). Controlled by a processor, this SRAM memory is surrounded by logic that enables it to perform efficient computations directly near the memory. Current application domains include Artificial Intelligence (AI) and cryptography, particularly post-quantum cryptography (PQC). In this context, the CEA is exploring the testability of memories integrated into NMC systems, leveraging the existing computing capabilities in such architectures. In this intern, the aim is to evaluate the fault coverage of the C-SRAM and to propose a solution to increase it while limiting the hardware modifications.